주차 | 주차명 | 차시명 | 과제 |
1 | Courseoverview | Course introduction | 퀴즈(2) |
Calculator with simple ISA |
2 | Computerarchitecture | Simple ISA project1 | 퀴즈(2) |
Stored program, sequentialexecution |
More than Von Neumann Other computerarchitectures |
3 | Instruction Set Architecture and MIPSISA | Instruction Set Architecture andarchitectural state | 퀴즈(2) |
Instruction encoding and addressingmodes |
MIPS instruction execution engineimplementation |
4 | MIPSinstruction set architecture | Understandings of MIPS integerISA | 퀴즈(2) |
Arithmetic operations (R-type, I-type) |
MIPS instruction execution engineimplementation |
5 | MIPSsingle-cycle microarchitecture | The data path for MIPS R-type ALU &I-type ALU | 퀴즈(1) |
The data path for SW & LWinstruction |
The data path for brach &jump |
6 | MIPSmulti-cycle microarchitecture | MIPS Multi-Cyclearchitecture | 퀴즈(1) |
MIPS uarch MultiCycle |
7 | MIPSmulti-cycle microarchitecture / performanceconsiderations | Multi-Cycle MIPS An exampleexecution | 퀴즈(2) |
Measuring Performance How fast is yourCPU? |
8 | Pipelined MIPS –latched execution | uArch of MIPS, Latency analysis for pipelinedMIPS | 퀴즈(1) |
Possible problems with pipelined execution,Stall/pipeline inter-locking |
Pipeline simulation, extendingHW1 |
9 | Datadependency | Data dependency in pipelinedexecution | 퀴즈(2) |
MIPS: microprocessor without interlockingpipeline stages |
Data forwarding,scoreboarding |
10 | Controldependency | MIPS control dependency | 퀴즈(2) |
MIPS branch prediction |
MIPS dynamic branchprediction |
11 | Branchprediction &advanced pipeline | MIPS more than bp | 퀴즈(2) |
Memory hierarchy |
Cache basic |
12 | Cacheand memory hierarchy | Another cache structure | 퀴즈(2) |
Cache_Replacement_Policy |
Project4 |
13 | CacheReplacement & Write policy | Cache Write and Update | 퀴즈(1) |
Security and Architecture |
Semester Final |